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256-position one-time programmable dual-channel i 2 c digital potentiometers ad5172/ad5173 rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed . features 2-channel, 2 56- positi on otp (one-ti m e p r ogramma ble ) set-and-forget re sistan ce setting, low co st alternativ e to eemem unlimite d a d justments prior to otp activ a tion otp over writ e a l lows dyna mic a d justm e nts wit h us er def i ned pre s et end-t o -en d re si stance: 2. 5 k ? , 10 k ? , 50 k ? , 1 00 k ? compact m s op-10 (3 mm 4.9 mm) packag e fast settlin g tim e : t s = 5 s typ in pow e r- up full r ead/writ e of wip e r re giste r power-on pr ese t to mi dscale extra pack age a ddr es s deco de pins a d 0 and a d 1 (ad 517 3) single su pply 2. 7 v to 5. 5 v low temp eratu r e coefficient: 3 5 ppm/c low po wer, i dd = 6 a m a x wide oper ating temperat ure: C4 0c to +125 c evaluati on b o ar d an d softwar e are avai lable softwar e re plac es c in factory program m ing a pplicati o ns applic ation s system s c a libra t ion electronic s l e vel setting mechanical tri mmers? repl ace m ent in n e w de signs perman ent fact ory pc b setting transduc er a d ju stment of pre s sure, t e mper atur e, po sition , chemical, and o p tical sensors rf ampl ifier bia sing automotiv e ele c tronics a d just ment gain c o ntrol an d offset a d just ment general ov erview the ad5172/ad5173 a r e d u al c h a n n e l , 256-p o si tio n , on e-t i m e p r ogra mma b l e (o t p ) dig i tal p o t e n t io m e t e r s 1 th a t em p l o y fuse link te c h n o log y t o ac hie ve m e mo r y r e t e n t io n o f r e sis t a n ce s e t t i n g . o t p i s a c o st - e f f e c t i ve a l te r n a t iv e to e e m e m for u s e r s w h o do n o t ne e d to p r o g r a m t h e dig i t a l p o ten t i o m e ter s e t t in g i n me mor y more t h an o n c e . t h i s d e v i c e p e r f or ms t h e s a m e el e c - t r o n ic ad j u st m e n t f u n c t i o n as m e ch a n ic a l p o ten t iom e ters o r va r i a b le r e sis t o r s wi th en han c e d r e s o l u tio n , s o l i d-sta t e r e l i a b il- i t y , and s u p e r i o r lo w t e m p era t ure co ef f i cien t p e r f o r ma n c e . the ad5172/ad5173 a r e p r og ra mmed usin g a 2-wire , i 2 c co m p a t i b le dig i tal in t e r f ace . u n limi te d ad j u s t men t s a r e al lo w e d b e f o re p e r m a n e n t l y s e tt i n g t h e re s i st anc e v a lu e. d u r i ng ot p ac t i va t i o n , a p e r m a n en t b l o w f u s e co mmand f r e e z es t h e wi p e r p o si t i o n (a na lo go us t o placin g ep o x y o n a m e cha n ica l t r im me r). function al block di ag rams a1 v dd g nd sda scl w1 rdac register 1 serial input register 04103-0-001 b1 a2 w2 rdac register 2 b2 fuse links 12 / 8 f i g u re 1. a d 51 72 v dd g nd sda scl ad0 ad1 w1 rdac register 1 address decode serial input register b1 w2 rdac register 2 b2 fuse links 12 / 8 04103-0-002 f i g u re 2. a d 51 73 u n li k e tradi t io nal o t p dig i tal p o t e n t iom e t e rs, th e ad5172 / ad5173 ha ve a uniq ue t e m p o r ar y o t p o v er wr i t e f e a t ur e tha t a l lo ws fo r n e w a d j u st m e n t s e v e n a f t e r t h e f u s e has b e en b l o w n. h o w e v e r , t h e otp s e t t ing is r e st o r e d d u r i n g subs e q ue n t p o w e r - u p co n d i ti o n s. t h i s f e a t ur e allo w s use r s t o tr ea t th e s e d i gi tal p o te n t i o me te rs a s vol a t i l e p o te n t i o me te rs w i t h a pro g r a mmabl e p r es et. f o r a p p l ica t ion s tha t p r og ra m t h e ad5172 /ad5173 a t t h e f a c t or y , a n a l o g d e v i c e s of f e r s d e v i c e pro g r a m m i n g s o f t w a re r u nnin g o n w i n d o w s? nt?, 20 00, a n d xp? o p e r a t in g syst em s. t h i s s o f t w a re e f f e c t ively re p l a c e s an y e x te r n a l i 2 c co n t r o l l ers, t h us enhan c ing t h e t i me-t o - ma rk et o f t h e us er s sys t em s. 1 the te rms d i gital p o te ntio m e t e r, vr, a n d rda c are us ed i nte rchange a bl y.
ad5172/ad5173 rev. a | page 2 of 24 table of contents electrical characteristics2.5 k? ................................................. 3 electrical characteristics10 k?, 50 k?, 100 k? versions ....... 4 timing characteristics2.5 k?, 10 k?, 50 k?, 100 k? versions ............................................................................................................. 5 absolute maximum ratings............................................................ 6 typical performance characteristics ............................................. 7 test circuits..................................................................................... 11 operation......................................................................................... 12 one-time programming (otp) .............................................. 12 programming the variable resistor and voltage.................... 12 programming the potentiometer divider ............................... 13 esd protection ........................................................................... 14 terminal voltage operating range.......................................... 14 power-up sequence ................................................................... 14 power supply considerations................................................... 14 layout considerations............................................................... 15 evaluation software/hardware..................................................... 16 software programming ............................................................. 16 i 2 c interface .................................................................................... 18 i 2 c compatible 2-wire serial bus ........................................... 20 pin configuration and function descriptions........................... 22 outline dimensions ....................................................................... 23 ordering guide............................................................................... 24 revision history revision a 11/03data sheet changed from rev. 0 to rev. a change location changes to electrical characteristics2.5 k?......................... 3
ad5172/ad5173 rev. a | page 3 of 24 electrical characteristics2.5 k? table 1. v dd = 5 v 10% or 3 v 10%; v a = +v dd ; v b = 0 v; C40c < t a < +125c; unless otherwise noted parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect C2 0.1 +2 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect C6 0.75 +6 lsb nominal resistor tolerance 3 ?r ab t a = 25c C20 +55 % resistance temperature coefficient (?r ab /r ab )/?t v ab = v dd , wiper = no connect 35 ppm/c rwb (wiper resistance) r wb code = 0x00, v dd = 5 v 160 200 ? dc characteristicspotentiometer divider mode (specifications apply to all vrs) differential nonlinearity 4 dnl C1.5 0.1 +1.5 lsb integral nonlinearity 4 inl C2 0.6 +2 lsb voltage divider temperature coefficient (?v w /v w )/?t code = 0x80 15 ppm/c full-scale error v wfse code = 0xff C10 C2.5 0 lsb zero-scale error v wzse code = 0x00 0 2 10 lsb resistor terminals voltage range 5 v a , v b , v w gnd v dd v capacitance 6 a, b c a , c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance w c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 7 i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v otp supply voltage v dd_otp t a = 25c 6 6.5 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a otp supply current i dd_otp v dd_otp = 6 v, t a = 25c 100 ma power dissipation 8 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 30 w power supply sensitivity pss v dd = 5 v 10%, code = midscale 0.02 0.08 %/% dynamic characteristics 9 bandwidth C3 db bw_2.5k code = 0x80 4.8 mhz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.1 % v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 1 s resistor noise voltage density e n_wb r wb = 1.25 k?, r s = 0 3.2 nv/hz 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error, r-inl, is the deviatio n from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at vw with the rdac configured as a po tentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminals a, b, w have no limitations on polari ty with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the a terminal. the a terminal is open circuited in shutdown mode. 8 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 9 all dynamic characteristics use v dd = 5 v.
ad5172/ad5173 rev. a | page 4 of 24 electrical characteristics10 k?, 50 k?, 100 k? versions table 2. v dd = 5 v 10% or 3 v 10%; v a = v dd ; v b = 0 v; C40c < t a < +125c; unless otherwise noted parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect C1 0.1 +1 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect C2.5 0.25 +2.5 lsb nominal resistor tolerance 3 ?r ab t a = 25c C20 +20 % resistance temperature coefficient (?r ab /r ab )/?t v ab = v dd , wiper = no connect 35 ppm/c r wb (wiper resistance) r wb code = 0x00, v dd = 5 v 160 200 ? dc characteristicspotentiometer divider mode (specifications apply to all vrs) differential nonlinearity 4 dnl C1 0.1 +1 lsb integral nonlinearity 4 inl C1 0.3 +1 lsb voltage divider temperature coefficient (?v w /v w )/?t code = 0x80 15 ppm/c full-scale error v wfse code = 0xff C2.5 C1 0 lsb zero-scale error v wzse code = 0x00 0 1 2.5 lsb resistor terminals voltage range 5 v a , v b , v w gnd v dd v capacitance 6 a, b c a , c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance 6 w c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 7 i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v otp supply voltage 8 v dd_otp 6 6.5 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a otp supply current 9 i dd_otp 100 ma power dissipation 10 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 30 w power supply sensitivity pss v dd = +5 v 10%, code = midscale 0.02 0.08 %/% dynamic characteristics 11 bandwidth C3 db bw r ab = 10 k?, code = 0x80 600 khz r ab = 50 k?, code = 0x80 100 khz r ab = 100 k?, code = 0x80 40 khz total harmonic distortion thd w v a =1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k? 0.1 % v w settling time (10 k?/50 k?/100 k?) t s v a = 5 v, v b = 0 v, 1 lsb error band 2 s resistor noise voltage density e n_wb r wb = 5 k?, r s = 0 9 nv/hz 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error, r-inl, is the deviatio n from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminals a, b, w have no limitations on polari ty with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the a terminal. the a terminal is open circuited in shutdown mode. 8 different from operating power supply, po wer supply otp is us ed one time only. 9 different from operating current, supply current fo r otp lasts approximately 400 ms for one time only. 10 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 11 all dynamic characteristics use v dd = 5 v.
ad5172/ad5173 rev. a | page 5 of 24 timing characteristics2.5 k?, 10 k?, 50 k?, 100 k? versions table 3. v dd = 5 v 10% or 3v 10%; v a = v dd ; v b = 0 v; C40c < t a < +125c; unless otherwise noted parameter symbol conditions min typ max unit i 2 c interface timing characteristics 1 (specifications apply to all parts) scl clock frequency f scl 400 khz t buf bus free time between stop and start t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period, the first clock pulse is generated. 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 s t su;sta setup time for repeated start condition t 5 0.6 s t hd;dat data hold time 2 t 6 0.9 s t su;dat data setup time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su;sto setup time for stop condition t 10 0.6 s 1 see timing diagrams for lo cations of measured values. 2 the maximum t hd;dat has only to be met if the device does not stretch the low period (t low ) of the scl signal.
ad5172/ad5173 r e v. a | pa ge 6 o f 2 4 absolute maximum ra tings table 4. t a = 2 5 c, u n les s ot herwi s e not e d p a r a m e t e r v a l u e v dd to gnd C0.3 v to +7 v v a , v b , v w to g n d v dd terminal current, axCbx, axCwx, bxCwx 1 pulsed 2 0 m a c o n t i n u o u s 5 m a digital inputs and output vo ltage to gnd 0 v to 7 v operating tem p erature range C40c to +125c maximum junction temperature (t jma x ) 1 5 0 c storage temperature C65c to +150c lead temperature (soldering, 10 sec) 300c t h ermal resista n ce 2 ja : msop-1 0 230c/w 1 maximum terminal current is bound b y the maximum cur r ent handling of the s w itches , maxi m um power d i ss ip ation of the package, and maximum appl ied vol t age acros s any two of the a , b, and w terminal s at a given resi st a n ce. 2 pa cka g e pow e r di s s i p a t i o n = (t jm ax C t a )/ ja . s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad5172/ad5173 r e v. a | pa ge 7 o f 2 4 typical perf orm ance cha r acte ristics ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 0.5 rheostat mode inl (lsb) 1.0 1.5 2.0 128 96 32 6 4 0 1 60 1 9 2 22 4 2 56 code (decimal) 04103-0-003 v dd = 5.5v t a = 25 c r ab = 10k ? v dd = 2.7v f i gur e 3 . r - inl vs . co de vs . sup p l y v o l t a g e s ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rhe os tat mode dnl (ls b ) 128 96 32 6 4 0 1 60 1 9 2 22 4 2 56 code (decimal) 04103-0-004 t a = 25 c r ab = 10k ? v dd = 2.7v v dd = 5.5v f i gur e 4 . r - dnl vs . c o de vs . sup p l y v o lta g e s ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 p o te ntiome te r mode inl (ls b ) 128 96 32 6 4 0 1 60 1 9 2 22 4 2 56 code (decimal) 04103-0-005 r ab = 10k ? v dd = 2.7v t a = ? 40c, +25c, +85c, +125c v dd = 5.5v t a = ? 40 c, +25 c, +85c, +125c f i gur e 5 . inl vs . code vs . t e m p e r a t ur e ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 p o te ntiome te r mode dnl (ls b ) 128 96 32 6 4 0 1 60 1 9 2 22 4 2 56 code (decimal) 04103-0-006 v dd = 2.7v; t a = ? 40c, +25c, +85 c, +125c r ab = 10k ? f i gur e 6 . dnl vs . c o de vs . t e m p e r a t ur e ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 p o te ntiome te r mode inl (ls b ) 128 96 32 6 4 0 1 60 1 9 2 22 4 2 56 code (decimal) 04103-0-007 t a = 25 c r ab = 10k ? v dd = 2.7v v dd = 5.5v f i gur e 7 . inl vs . code vs . sup p l y v o l t age s ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 p o te ntiome te r mode dnl (ls b ) 128 96 32 6 4 0 1 60 1 9 2 22 4 2 56 code (decimal) 04103-0-008 t a = 25 c r ab = 10k ? v dd = 2.7v v dd = 5.5v f i gur e 8 . dnl vs . c o de vs . sup p l y v o l t a g e s
ad5172/ad5173 r e v. a | pa ge 8 o f 2 4 ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 0.5 rheostat mode inl (lsb) 1.0 1.5 2.0 128 96 32 6 4 0 1 60 1 9 2 22 4 2 56 code (decimal) 04103-0-009 r ab = 10k ? v dd = 2.7v t a = ? 40c, +25c, +85 c, +125 c v dd = 5.5v t a = ? 40 c, +25 c, +85c, +125c f i gur e 9 . r - inl vs . co de vs . t e m p e r a t ur e ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rhe os tat mode dnl (ls b ) 128 96 32 6 4 0 1 60 1 9 2 22 4 2 56 code (decimal) 04103-0-010 v dd = 2.7v, 5.5v; t a = ? 40 c, +25 c, +85c, +125c r ab = 10k ? f i gur e 1 0 . r - dnl vs . c o de vs . t e m p e r a t ur e ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 0.5 fse, fu ll- sc a l e er r o r ( l sb ) 1.0 1.5 2.0 temperature ( c) ? 4 0 ? 25 ?10 5 20 35 50 65 80 95 110 125 04103-0-011 v dd = 5.5v, v a = 5.0v r ab = 10k ? v dd = 2.7v, v a = 2.7v f i gure 11. f u ll- s c al e e rror v s . t e m p er a t ur e 0 0.75 1.50 2.25 3.00 3.75 4.50 zs e , ze ro-s cale e rror (ls b ) temperature ( c) ? 4 0 ? 25 ?10 5 20 35 50 65 80 95 110 125 04103-0-012 v dd = 5.5v, v a = 5.0v r ab = 10k ? v dd = 2.7v, v a = 2.7v f i gure 12. zero -s c a le e r r o r v s . t e mpe r a t ur e i dd , s u p p l y curre nt ( a) 0.1 1 10 ?40 ? 7 2 6 5 9 9 2 125 temperature ( c) 04103-0-013 v dd = 5v v dd = 3v f i gure 13. sup p l y current v s . t e mper at ur e ?20 0 20 40 60 80 100 120 rheostat mode te mp co (ppm/c) 128 96 32 6 4 0 1 60 1 9 2 22 4 2 56 code (decimal) 04103-0-014 r ab = 10k ? v dd = 2.7v t a = ? 40 c to +85c, ? 40c to +125c v dd = 5.5v t a = ? 40 c to +85c, ? 40c to +125c f i g u re 14. r h e o s t at m o de t e mpco ?r wb /?t v s . code
ad5172/ad5173 r e v. a | pa ge 9 o f 2 4 ?30 ?20 ?10 0 10 20 p o te ntiome te r mode te mp co (ppm/ c) 30 40 50 128 96 32 6 4 0 1 60 1 9 2 22 4 2 56 code (decimal) 04103-0-047 r ab = 10k ? v dd = 2.7v t a = ? 40c to +85c, ? 40c to +125c v dd = 5.5v t a = ? 40c to +85 c, ? 40 c to +125c f i gur e 1 5 . ad51 72 p o t e nt i o m e t e r mode t e m p c o ? v wb /?t vs . c o de ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 10k 1m 100k 10m 04103-0-048 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 16. g a in vs. f r equ e nc y vs. c o d e , r ab = 2. 5 k ? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 1k 100k 10k 1m 04103-0-049 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 17. g a in vs. f r equ e nc y vs. c o d e , r ab = 10 k? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 1k 100k 10k 1m 04103-0-050 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 18. g a in vs. f r equ e nc y vs. c o d e , r ab = 50 k? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 1k 100k 10k 1m 04103-0-051 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 19. g a in vs. f r equ e nc y vs. c o d e , r ab = 10 0 k? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 10k 1k 100k 1m 10m 04103-0-052 100k ? 60khz 50k ? 120khz 10k ? 570khz 2.5k ? 2.2mhz f i gure 20. C3 db bandwidth @ code = 0x80
ad5172/ad5173 rev. a | page 10 of 24 i dd , s u p p l y curre nt (ma) 0.01 1 0.1 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 digital input voltage (v) 04103-0-057 t a = 25 c v dd = 2.7v v dd = 5.5v f i g u re 21. i dd vs . input v o l t a g e 04103-0-053 scl v w f i gure 2 2 . di g i ta l f eedthro u g h 04103-0-054 v w1 v w2 f i g u re 23. d i g i t a l c r os s t a l k 04103-0-056 v w1 v w2 f i g u re 24. a n a l og cr os s t alk 04103-0-058 v w f i g u re 25. m i ds c a l e gli t ch, cod e 0x 80 t o 0x 7f 04103-0-055 scl v w f i gure 2 6 . la r g e s i gna l s e ttli n g t i m e
ad5172/ad5173 rev. a | page 11 of 24 test circuits f i gur e 27 t o f i gur e 34 il l u s t ra t e th e t e s t cir c ui ts tha t def i n e t h e t e st con d i t io ns us e d in t h e p r o d uc t sp e c if ic a t i o n t a b l es. 04103-0-015 v ms a w b dut v+ v + = v dd 1lsb = v + / 2 n f i gure 27. t e s t c i rc uit for p o tenti o meter d i v i de r n o nl in ea rit y e r r o r (inl, dnl) 04103-0-016 no connect i w v ms a w b dut f i gure 28. t e s t c i rc uit for r e s i s t or p o s i tion non l i n e a r i t y e rror (r heo s ta t o p er a t ion; r - inl, r - dnl) 04103-0-017 v ms1 i w = v dd /r nominal v ms2 v w r w = [v ms1 ? v ms2 ]/ i w a w b dut f i gur e 2 9 . t e st c i r c ui t fo r wi p e r resi st a n c e 04103-0-018 ? v ms % dd % pss (% / %) = v+ = v dd 10% psrr (db) = 20 log dut ms dd ( ) v dd v a v ms a w b v+ ? v ? v ? v f i gure 30. t e st c i rc uit for p o w e r sup p l y s e nsit ivit y ( p ss, pssr) 04103-0-019 +15v ?15v w a 2.5v b v out offset gnd dut ad8610 v in f i gure 31. t e s t c i rc uit for g a in v s . f r eq uenc y 04103-0-020 w b dut i sw code = 0x00 r sw = 0.1v i sw 0.1v gnd to v dd f i gu r e 3 2 . t e st ci r c u i t fo r i n cr em en ta l on re si sta n c e 04103-0-021 v dd a w b dut gnd i cm v cm nc nc f i g u re 33. t e s t c i rc uit f o r co m m o n -m ode l e ak ag e cur r e n t 04103-0-022 v in n/c w1 b1 b2 w2 rdac1 a1 rdac2 v dd v ss v out cta = 20 log[v out /v in ] a2 f i gur e 3 4 . t e st c i r c ui t fo r a n al o g c r o ssta l k
ad5172/ad5173 rev. a | page 12 of 24 ope ra tion sda scl a w b fuses en dac reg. i 2 c interface comparator one-time program/test control block mux decoder fuse reg. 04103-0-026 f i g u re 35. d e t a iled f u nc t i on al bl ock d i ag r a m the ad5172/ad5173 is a 256-p o si tio n , dig i tal l y co n t r o l l ed va r i a b le r e sis t o r (vr) tha t e m p l o y s fus e link te chn o log y t o a c h i e v e me mor y re te n t i o n of re s i st an c e s e tt i n g . an in t e r n al p o w e r - o n p r es et places t h e wi p e r a t mids cale d u ri n g po w e r - o n . i f th e o t p fun c ti o n h a s been a c ti v a t e d , t h e de vice p o w e rs u p a t t h e us er - d e f in e d p e r m an e n t s e t t ing. one- time progr a mming ( o tp) p r io r t o o t p ac ti va tion, the ad5172/ad5173 p r es ets t o mid- s c a l e d u r i n g ini t ia l p o w e r - on. af t e r t h e w i p e r is s e t a t t h e desir e d p o si tion, th e r e sis t an ce c a n be p e r m an e n tl y s e t b y p r og ra mmin g t h e t b i t hig h al o n g w i t h t h e p r o p er co di n g (s e e t a b l e 5 an d t a ble 6). n o t e tha t f u s e link tec h n o log y r e q u ir es 6 v t o b l o w t h e i n t e r n al f u s e s t o achie v e a g i v e n s e t t ing. th e us er i s a l l o we d on ly on e atte m p t a t bl ow i n g t h e f u s e s . o n c e pro g r a m - ming is c o m p l e te d, t h e p o we r sup p ly vol t age m u st b e re d u c e d to th e n o r m al o p era t in g ra n g e o f 2.7 v t o 5.5 v . the device con t r o l cir c ui t has tw o valida tio n b i ts, e1 a nd e0, tha t c a n be r e ad bac k t o ch eck th e p r og ra mming s t a t us (s ee t a b l e 7). u s ers sh o u ld al wa ys r e ad ba ck th e v a lida ti o n b i t s t o en s u r e t h a t t h e f u s e s a r e p r o p erl y b l o w n. af t e r t h e f u s e s ha v e be e n b l o w n, al l f u s e la t c h e s a r e ena b le d u p o n su bs e q ue n t p o we r - on ; t h e r e f ore, t h e output c o r r e s p o nd s to t h e s t ore d s e t t in g. f i gur e 3 5 s h o w s a deta il ed f u n c tio n al b l o c k dia g ram. progr a mm ing the v a riable resi st or and vo l t a g e r h eos t at ope r ation the n o minal r e sis t a n ce o f the rd a c be tw e e n t e r m inals a and b is a v a i la b l e in 2.5 k?, 10 k?, 50 k?, a nd 100 k?. th e n o minal re s i st anc e ( r ab ) o f th e vr has 2 56 co n t ac t p o in ts acces s e d b y t h e w i p e r t e r m i n al , pl us t h e b ter m inal co n t ac t. the 8- b i t da t a in t h e rd a c l a tc h is deco ded t o s e lec t on e o f the 256 p o s s i b le se t t in g s . a w b a w b a w b 04103-0-027 f i g u re 36. r h e o s t at m o de conf ig ur at i o n a ssu min g a 10 k? p a r t is us e d , t h e wi p e r s f i rst co nne c t io n s t a r ts a t t h e b t e r m inal fo r da t a 0x00. b e ca us e t h er e is a 50 ? wi p e r co n t ac t r e sist a n ce, such a co nne c t io n y i el ds a mi nim u m o f 100 ? (2 5 0 ?) r e sis t a n ce betw een t e r m inals w an d b . the s e con d co n n e c t i o n is t h e f i rst t a p p o in t, w h ich c o r r esp o n d s t o 139 ? (r wb = r ab /256 + 2 r w = 39 ? + 2 5 0 ?) f o r da ta 0x01. th e t h ird co nne c t io n is t h e n e xt t a p p o in t, r e p r es en t i n g 178 ? (2 39 ? + 2 50 ?) f o r da ta 0x02, an d s o o n . e a c h ls b da t a v a l u e in cr e a s e m o v e s t h e w i p e r u p t h e r e sist o r ladder un t i l th e l a s t ta p p o in t is r e ac h e d a t 1 0 ,100 ? (r ab + 2 r w ). d5 d4 d3 d7 d6 d2 d1 d0 rdac latch and decoder r s r s r s r s a w b 04103-0-028 f i gur e 3 7 . ad51 72 /ad5 17 3 e q ui v a l e nt rd a c cir c ui t
ad5172/ad5173 rev. a | page 13 of 24 t h e g e n e ral eq ua ti o n tha t d e t e r m in e s th e d i g i ta ll y p r ogra m m ed o u t p u t r e s i s t a n ce bet w een w a n d b i s w ab wb r r d d r + = 2 128 ) ( ( 1 ) wher e d is the decim a l e q ui val e n t o f the b i na r y co de lo aded in t h e 8- b i t r d a c r e g i st er , r ab is t h e e n d- to -e n d resist a n ce, an d r w is th e wi p e r r e sis t a n c e co n t r i b u t e d b y th e o n r e sis t an ce o f th e in t e rn al swi t c h . i n s u mm a r y , if r ab = 10 k? a n d t h e a t e r m ina l is o p en- c i rc u i te d, t h e output re s i st a n c e r wb is s e t fo r t h e rd a c la t c h co des, as sh o w n in t a b l e 5. ta ble 5. co des a nd corr es po n d i n g rwb res i s t a n ce d (dec.) r wb (?) output state 2 5 5 9 , 9 6 1 full-scale (r ab C 1 lsb + r w ) 1 2 8 5 , 0 6 0 m i d s c a l e 1 1 3 9 1 l s b 0 100 zero-scale (wiper contact resistance) n o t e tha t in t h e zer o -s cale co n d i t io n, a f i ni te wi p e r r e sis t a n c e o f 100 ? is p r es en t. c a r e s h o u ld be tak e n t o limi t t h e c u r r en t f l o w b e tw e e n w and b in t h is st a t e t o a maxim u m p u ls e c u r r en t o f n o m o r e tha n 2 0 m a . other w is e , d e grada t io n o r p o s s i b le des t r u c t io n o f th e in t e r n al s w i t c h co n t ac t can o c c u r . si mi l a r to t h e me chani c a l p o te n t i o me te r , t h e re s i st anc e of t h e r d a c betw een th e wi per w a n d t e rm i n al a als o p r od uces a dig i t a l l y co n t r o l l ed co m p lem e n t a r y r e sis t a n ce , r wa . w h e n t h es e t e r m ina l s a r e us e d , t h e b t e r m ina l ca n b e op e n e d . s e t t in g t h e re s i st anc e v a lu e f o r r wa st ar ts a t a max i m u m va lue o f r e sist anc e a n d de cr e a s e s a s t h e d a t a lo ade d in t h e la t c h incr eas e s in va l u e . the ge n e ra l e q u a t i o n fo r t h is o p era t io n is w ab wa r r d d r + = 2 128 C 256 ) ( ( 2 ) fo r r ab = 10 k? a n d t h e b t e r m i n al o p en-cir c u i t e d , t h e f o l l ow i n g output re s i st anc e r wa is s e t f o r th e rd a c la t c h co des, as sh o w n in t a ble 6. ta ble 6. co des a nd corr es po n d i n g r wa resist an ce d (dec.) r wa (?) output state 2 5 5 1 3 9 f u l l - s c a l e 1 2 8 5 , 0 6 0 m i d s c a l e 1 9 , 9 6 1 1 l s b 0 1 0 , 0 6 0 z e r o - s c a l e t y p i cal de vice-to-de vice m a t c hin g is p r o c es s lo t dep e n d en t and ma y va r y b y u p t o 30%. b e c a us e t h e r e sist an ce e l em e n t is p r o- ces s ed usin g t h in f i lm t e chn o log y , th e c h a n g e in r ab wi t h t e m p era t ur e has a v e r y lo w 35 p p m/ c t e m p er a t ur e co ef f i cien t. progr a mm ing the po tent iome t e r divi der voltage o u tp ut ope r ation the di g i t a l p o te n t i o me te r e a s i ly ge ne r a te s a volt age d i v i de r a t wip e r - to - b and wip e r - to - a prop or t i ona l to t h e i n pu t volt age a t a- t o - b . un l i k e t h e p o l a r i t y o f v dd t o gnd , which m u st b e p o si - ti v e , v o l t a g e a c r o s s a - b , w - a , a n d w - b ca n be a t ei th e r po la ri ty . a v i w b v o 04103-0-029 f i gure 38. p o tentiometer m o de c o nf ig ur ation i f ig n o r i n g t h e e f fe c t o f t h e wi p e r r e sist a n ce fo r a p p r o x ima t ion, co nne c t in g t h e a t e r m ina l t o 5 v a n d t h e b ter m ina l t o g r o u nd p r o d uces a n o u t p u t v o l t a g e a t the wi p e r - t o -b star tin g a t 0 v u p t o 1 ls b les s than 5 v . e a c h ls b o f v o l t a g e is eq ual t o th e v o l t a g e a p p l ie d acr o s s t e r m inal ab divided b y t h e 256 p o si t i o n s o f t h e p o te n t iom e ter divider . t h e ge n e r a l e q u a t i o n def i n i n g t h e output vo lt ag e at v w wi t h r e s p e c t t o gr o u n d f o r a n y valid in p u t v o l t a g e a p plie d t o t e r m ina l s a and b is b a w v d v d d v 256 256 256 ) ( ? + = ( 3 ) f o r a m o r e acc u ra t e c a lc u l a t ion, which i n cl udes t h e ef fe c t o f wip e r r e sist an ce, v w ca n be f o und as b ab wa a ab wb w v r d r v r d r d v ) ( ) ( ) ( + = ( 4 ) o p era t ion o f t h e dig i t a l p o ten t i o m e t e r in t h e divider m o de re su lt s i n a more a c c u r a te o p e r at i o n ove r te m p e r a t u r e. u n l i ke t h e rh e o s t a t m o de , t h e o u t p u t vol t a g e is de p e n d en t mainly o n th e ra ti o o f th e in t e rn al r e s i s t o r s r wa and r wb and n o t t h e a b s o - l u t e val u es. th us, t h e t e m p er a t ur e dr if t r e d u ces t o 15 p p m / c.
ad5172/ad5173 rev. a | page 14 of 24 esd pro t ec tion all d i gi tal i n p u tss d a , sc l, ad 0, a n d ad 1 a r e p r o t ect e d w i t h a s e r i e s i n put re s i stor an d p a r a l l el z e ne r e s d st r u c t u r e s , a s s h o w n i n fi g u r e 3 9 a n d fi g u r e 4 0 . logic 340 ? gnd 04103-0-030 f i g u re 39. e s d pr ot ec t i o n of d i g i t a l p i ns a,b,w gnd 04103-0-031 f i g u re 40. e s d pr ot ec t i o n of r e s i s t o r t e r m in als terminal vol t a g e o p e r a t ing r a nge the ad5172/ad5173 v dd t o gnd p o w e r s u p p l y def i n e s t h e bo u n da r y co n d i t io n s f o r p r o p er 3-t e r m inal dig i tal p o t e n t iom- et er o p era t ion. s u p p ly sig n als p r es en t o n t e r m i n als a, b , a n d w th a t e x ceed v dd o r gnd a r e cl am p e d b y t h e in ter n al fo r w a r d- b i as e d dio d es (s ee f i gur e 41). gnd a w b v dd 04103-0-032 f i g u re 41. m a x i mu m t e r m i n a l v o lt ag es s e t by v dd and g nd power-up sequence b e ca us e t h e esd p r o t e c t i on di o d es limi t t h e vol t a g e com p li ance a t t e r m inals a, b , a n d w (s e e f i gur e 41), i t is im p o r t a n t t o po w e r v dd /gnd bef o r e a p p l yin g an y v o l t a g e to t e r m inals a, b , a n d w . oth e r w is e , th e dio d e wil l be f o r w a r d b i as ed s u ch tha t v dd is p o w e r e d unin ten t io n a l l y a n d m a y a f fe c t t h e r e st o f t h e us er s cir c ui t. th e ideal p o w e r - u p s e q u en ce is gnd , v dd , t h e dig i t a l in p u ts, and t h e n v a /v b /v w . t h e rel a t i v e ord e r of po w e ri n g v a , v b , v w , a n d t h e di g i t a l i n p u ts is no t im p o r t a n t as l o ng a s t h e y are p o we re d af te r v dd /gnd . po wer sup p l y c o nsi d er a t ions t o m i n i m i z e th e pa c k a g e p i n co u n t , b o th th e o n e - t i m e p r o - g r a mmin g and n o r m al o p er a t i n g v o l t a g e s u p p l i es a r e a p plie d to th e sa m e v dd t e r m inal o f th e ad5172/ad5173. th e ad5172 / ad5173 em p l oy f u s e link t e c h n o log y tha t r e q u ir es 6 v t o b l o w t h e i n t e r n al f u s e s t o achie v e a g i v e n s e t t i n g. the us er is al lo w e d on ly one atte m p t a t bl ow i n g t h e f u s e s . o n c e pro g r a m m i ng i s co m p let e d , p o w e r s u p p l y v o l t a g e m u s t be r e d u c e d t o t h e n o r m a l 2.7 v t o 5.5 v o p era t i n g ra n g e . s u ch d u al v o lt ag e r e q u ir emen t s r e q u ir e is ola t ion b e twe e n t h e su p p lies. th e f u s e p r og ra mmin g supply ( e it he r a n on - b o a rd re g u l a tor or r a ck - m ou n t p o we r s u p - p l y) m u s t be r a ted a t 6 v and m u s t be ab le t o p r o v ide a 100 ma tra n sien t c u r r en t f o r 400 m s f o r s u cces s f u l o n e-t i me p r og ra m- ming. on c e p r og ra mmin g is com p let e , t h e 6 v s u p p l y m u s t be r e m o v e d t o al lo w n o r m al o p era t io n a t 2.7 v t o 5.5 v a t r e gu l a r micr o a m p c u r r en t leve ls. f i gur e 42 s h o w s t h e s i m p les t im p l e- m e n t a t io n using a j u m p er . this a p p r o a ch s a v e s o n e v o l t a g e s u p p ly , b u t dra w s addi t i o n al c u r r en t a n d r e q u ir es ma n u al co nf igura t io n. v dd 6v r1 50k ? r2 c1 1 f c2 1nf 250k ? 5v connect j1 here for otp connect j1 here after otp ad5172/ ad5173 04103-0-033 f i g u re 42. p o wer s u p p ly r e qu ire m ent an al t e r n a t e a p p r o a c h in 3.5 v t o 5.5 v sys t em s adds a sig n al dio d e b e tw e e n t h e syst em s u p p ly a n d t h e o t p su p p ly fo r is ola t ion, as sh o w n in f i gur e 43. v dd 3.5v?5.5v 6v d1 c1 1 f c2 1nf apply for otp only ad5172/ ad5173 04103-0-034 f i g u re 43. is ol at e 6 v o t p sup p l y f r om 3.5 v to 5. 5 v no rm al o p er at ing sup p ly . th e 6 v s u p p ly m u s t be r e m o ved on c e o t p is co m p let e d .
ad5172/ad5173 rev. a | page 15 of 24 v dd 2.7v 6v p1 p1=p2=fdv302p, nds0610 r1 10k ? p2 c1 1 f c2 1nf apply for otp only ad5172/ ad5173 04103-0-035 p o o r pcb l a yo u t in tr o d uces p a rasi tics tha t ma y a f f e c t th e f u s e p r o g r a mmin g . ther efo r e , i t is r e co m m e n de d to add a 1 f ta n t a l um ca p a c i t o r in p a ral l e l wi th a 1 nf ceramic ca p a c i t o r as clos e as p o s s i b le t o t h e v dd p i n. th e s e c a p a ci t o rs h e l p en s u r e otp p r og ra mm in g success b y pr o v idin g p r o p er c u r r en t den s i- ties. this com b ina t ion o f ca p a c i t o r val u es p r o v ides bo t h a fas t re sp ons e f o r h i g h f r e q u e nc y t r a n s i e n t s an d a l a r g e r supply of c u r r en t fo r ext e n de d sp i k es. t y p i cal l y , c1 min i mi zes an y t r a n sien t dist urb a nces an d lo w f r e q uen c y r i p p le , w h i l e c2 re d u c e s h i g h f r e q u e nc y noi s e. f i g u re 44. is ol at e 6 v o t p sup p l y f r om 2.7 v n o r m a l o p e r at ing su p p ly . the 6 v sup p l y m u s t be rem o ved once o t p is comp le ted . l a y o ut c o nsider a t i o ns i t is a g o o d p r ac tice t o em p l o y co m p ac t, minim u m lead len g t h la yo u t desig n . th e le ads t o t h e in p u ts sh o u ld be as dir e c t as pos s i b le wi th a m i n i m u m co n d uct o r le n g th . g r o u n d p a th s s h o u ld ha v e lo w r e sis t a n ce an d l o w ind u c t an ce . f o r us ers w h o o p era t e t h e i r sys t em s a t 2.7 v , us e o f t h e bi d i re c t i o n a l l o w t h re sho l d p - c h mo sf e t s i s re c o m m e n d e d fo r t h e su p p ly s is ola t ion. a s sh o w n in f i gur e 44, t h is assu m e s t h a t t h e 2.7 v sy s t em v o lt a g e is a p plie d f i rs t, and t h a t t h e p1 and p2 ga t e s a r e p u l l ed t o g r o u nd , th us t u r n in g on p1 a n d subs e q u e n t ly p 2 . a s a re su lt , v dd o f th e ad517 2/ad5173 a p p r o a c h es 2.7 v . w h en t h e ad5172/ad5173 s e t t in g is f o und, th e fa c t o r y t e s t er a p p l i e s th e 6 v t o v dd ; t h e 6 v is als o a p plie d t o th e g a t e s o f p 1 a n d p2 t o t u r n them o f f . th e o t p command is exec u t ed a t this time t o p r og ra m t h e ad5172 /ad5173; t h e 2.7 v s o ur ce is th er ef o r e p r o t ec ted . on ce t h e otp is com p let e d, th e t e s t er wi t h dra w s t h e 6 v and the ad5172/ad5173 s s e t t ing is f i xe d p e r m a n en t l y . n o t e tha t t h e dig i tal g r o u nd sho u ld als o be jo in e d r e m o t e l y t o t h e an a l o g g roun d a t o n e p o i n t to m i n i m i z e t h e g rou nd b o u n c e . v dd gnd v dd c1 1 f c2 1nf ad5172 + 04103-0-036 ad5172/ad51 73 ac hiev es t h e o t p f u n c tion t h r o u g h b l o w ing in t e r n al f u s e s. u s ers s h o u ld alw a ys a p ply t h e 6 v o n e-t i me p r og ra m v o l t a g e r e q u ir emen t a t t h e f i rs t p r og ra m co mman d . f a il ur e t o co m p l y wi th t h is r e q u ir em en t ma y lead t o t h e c h ang e o f f u s e s t r u c t ur es, r e n d er in g p r og ra mmin g i n op era b le . f i g u r e 4 5 . p o w e r su pp l y by pa s s i n g
ad5172/ad5173 rev. a | page 16 of 24 ev alua tion softw a re/hardw are f i gur e 4 6 . ad51 72 /ad5 17 3 c o m p ute r so f t w a r e int e r f a c e ther e a r e tw o wa ys o f co n t r o l l in g th e ad5172 /ad5173. u s ers ca n ei t h er p r og ra m t h e de vices wi t h com p u t er s o f t wa r e o r wi t h ext e r n al i 2 c co n t r o l l ers. soft w a re progr a mm ing d u e t o t h e ad van t a g es o f t h e one-t i m e p r og ra mma b le fe a t ur e , us ers ma y co n s ider p r og ra mmin g t h e de vic e i n t h e fac t o r y b e fo r e s h i p p i n g t h e f i nal p r o d uc t t o end-us ers. ad i o f fers a de vice p r og ra mmin g s o f t wa r e t h a t c a n be im p l em en t e d in t h e f a c t or y on p c s r u n n i ng w i n d ow s 9 5 or l a te r . as a re su lt , ext e r n a l co n t r o l l ers a r e n o t r e quir e d , w h ich sig n if ican t l y r e d u ces de v e l o p m e n t time . th e p r og ra m is a n exec u t a b le f i le t h a t d o e s no t re qu i r e a n y pro g r a m m i ng l a ng u a ge s or u s e r p r og ra mmin g skil ls. i t is easy t o s e t u p an d t o us e . f i gur e 46 show s t h e s o f t w a re i n te r f a c e. t h e s o f t w a re c a n b e d o w n l o a d e d fr o m www .a n a lo g . c o m . the ad5172/ad5173 s t a r ts a t mids cale a f t e r p o w e r - u p p r io r t o o t p p r ogra m m i n g . t o in cr em en t o r d e cr em en t th e r e s i s t a n ce , t h e us er ma y sim p ly m o v e t h e s c r o l l b a rs o n t h e lef t . t o wr i t e a n y sp e c if ic value , t h e us er sh ou ld us e t h e b i t p a t t e r n i n t h e u p p e r s c r e en and p r es s t h e r u n b u t t on. th e fo r m a t o f wr i t in g da ta t o th e de vice is sh o w n in t a b l e 7. on c e the desir e d s e t t ing is fo un d , t h e us e r ma y p r es s t h e p r og ra m p e r m a m e n t b u t t o n t o b l o w th e in t e r n al f u s e links. t o re a d t h e v a l i d a t i on bit s a n d d a t a out f rom t h e d e v i c e , t h e us er sim p ly p r es s e s t h e re ad b u t t o n . th e fo r m a t o f t h e r e ad b i ts is sh own i n t a b l e 8. t o a p p l y th e de vice p r og ra mmin g s o f t wa r e in t h e fac t o r y , us ers m u s t m o dif y a p a ral l e l p o r t ca b l e an d conf igur e p i n s 2, 3, 15, a n d 2 5 f o r s d a _ w r i t e , s c l , s d a _ r e a d , a n d d g n d , r e s p e c t i v e l y , fo r t h e co n t r o l sig n als (f igur e 47). u s ers sh o u ld als o la y o u t t h e pcb o f th e ad5 172/ad5173 wi th scl and s d a p a ds, as sh o w n in f i gur e 48, s u c h tha t p o g o p i n s can b e ins e r t ed f o r fac t o r y p r ogra m m i n g .
ad5172/ad5173 rev. a | page 17 of 24 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 scl r3 100 ? r2 100 ? r1 100 ? sda read write 04103-0-037 ad5172 ad5173 w1 b2 a2 sda scl b1 ad0 w2 gnd vdd b1 a1 w2 gnd vdd w1 b2 ad1 sda scl 04103-0-038 f i gur e 4 8 . re c o mme nde d ad5 172 / a d5 17 3 p c b la yo ut. the scl a n d sd a pads allo w pog o pins t o b e inser t ed s o t h at s i g n als c a n be c o m m un ic ated thr o u g h the par a l l el por t fo r prog r a m m ing ( f ig u r e 4 7 ) . f i g u re 47. p a r a l l e l p o r t con n ec t i on. p i n 2 = sda _ w r it e , p i n 3 = scl, p i n 15 = s d a _ r e ad , and pin 2 5 = dgn d .
ad5172/ad5173 rev. a | page 18 of 24 i 2 c interface table 7. write mode ad5172 s 0 1 0 1 1 1 1 w a a0 sd t 0 ow x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte ad5173 s 0 1 0 1 1 ad1 ad0 w a a0 sd t 0 ow x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte table 8. read mode ad5172 s 0 1 0 1 1 1 1 r a d7 d6 d5 d4 d3 d2 d1 d0 a e1 e0 x x x x x x a p slave address byte instruction byte data byte ad5173 s 0 1 0 1 1 ad1 ad0 r a d7 d6 d5 d4 d3 d2 d1 d0 a e1 e0 x x x x x x a p slave address byte instruction byte data byte s = start condition p = stop condition a = acknowledge ad0, ad1 = package pin programmable address bits x = dont care w = write r = read a0 = rdac subaddress select bit sd = shutdown connects wiper to b terminal and open circuits the a terminal. it does not change contents of wiper register. t = otp programming bit. logic 1 programs the wiper permanently. ow = overwrite the fuse setting and program the digital potentiometer to a different setting. note that upon power-up, the digital potentiometer is preset to either midscale or fuse setting, depending on whether not the fuse link has been blown. d7, d6, d5, d4, d3, d2, d1, d0 = data bits. e1, e0 = otp validation bits. 0, 0 = ready to program. 1, 0 = fatal error. some fuses not blown. do not retry. discard this unit. 1, 1 = programmed successfully. no further adjustments possible.
ad5172/ad5173 rev. a | page 19 of 24 04103-0-039 t 1 t 2 t 3 t 8 t 8 t 9 t 9 t 6 t 4 t 7 t 5 t 2 t 10 ps s scl sda p f i g u re 49. i 2 c inter f a c e d e ta il ed ti mi ng di a g r a m 04103-0-040 scl start by master sda 01 1 frame 1 slave address byte 0 1111 frame 2 instruction byte ack by ad5172 r/w a0 sd 0 o w x x x 1 9 d7 d6 d5 d4 d3 ack by ad5172 frame 3 data byte 1 9 t stop by master 9 d2 d1 d0 ack by ad5172 f i g u re 50. w r it ing t o t h e r d a c r e g i s t e r a d5 17 2 04103-0-041 scl start by master sda 01 1 frame 1 slave address byte 0 1 1 ad1 ad0 frame 2 instruction byte ack by ad5173 r/w a0 sd 0 o w x x x 1 9 d7 d6 d5 d4 d3 ack by ad5173 frame 3 data byte 1 9 t stop by master 9 d2 d1 d0 ack by ad5173 f i g u re 51. w r it ing t o t h e r d a c r e g i s t e r a d5 17 3 04103-0-042 scl start by master sda 01 1 frame 1 slave address byte 0 111 1 frame 2 instruction byte ack by ad5172 r/w d7 d6 d4 d3 d2 d1 d0 1 9 e1 e0 x x x ack by master frame 3 data byte 1 9 d5 stop by master 9 xx x no ack by master f i g u re 52. r e ad ing d a t a f r o m a p r ev i o us ly s e lec t ed r d a c r e g i s t er in writ e m o de a d5 17 2 04103-0-043 scl start by master sda 01 1 frame 1 slave address byte 0 1 1 ad1 ad0 frame 2 instruction byte ack by ad5173 r/w d7 d6 d4 d3 d2 d1 d0 1 9 e1 e0 x x x ack by master frame 3 data byte 1 9 d5 stop by master 9 xx x no ack by master f i g u re 53. r e ad ing d a t a f r o m a p r ev i o us ly s e lec t ed r d a c r e g i s t er in writ e m o de a d5 17 3
ad5172/ad5173 rev. a | page 20 of 24 i 2 c compatible 2-wire serial bus the 2-wire i 2 c serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high (see figure 50 and figure 51). the following byte is the slave address byte, which consists of the slave address followed by an r/ w bit (this bit determines whether data is read from or written to the slave device). the ad5172 has a fixed slave address byte, whereas the ad5173 has two configurable address bits, ad0 and ad1 (see figure 50 and figure 51). the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master reads from the slave device. if the r/ w bit is low, the master writes to the slave device. 2. in the write mode, the second byte is the instruction byte. the first bit (msb) of the instruction byte is the rdac subaddress select bit. a logic low selects channel 1; a logic high selects channel 2. the second msb, sd, is a shutdown bit. a logic high causes an open circuit at terminal a while shorting the wiper to terminal b. this operation yields almost 0 ? in rheostat mode or 0 v in potentiometer mode. it is important to note that the shutdown operation does not disturb the contents of the register. when brought out of shutdown, the previ- ous setting is applied to the rdac. also, during shutdown, new settings can be programmed. when the part is returned from shutdown, the corresponding vr setting is applied to the rdac. the third msb, t, is the otp programming bit. a logic high blows the poly fuses and programs the resistor setting permanently. the fourth msb must always be at logic 0. the fifth msb, ow, is an overwrite bit. when raised to a logic high, ow allows the rdac setting to be changed even after the internal fuses have been blown. however, once ow is returned to a logic zero, the position of the rdac returns to the setting prior to overwrite. because ow is not static, if the device is powered off and on, the rdac presets to midscale or to the setting at which the fuses were blown, depending on whether or not the fuses have been permanently set already. the remainder of the bits in the instruction byte are dont cares (see figure 50 and figure 51). after acknowledging the instruction byte, the last byte in write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 49). 3. in the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference from the write mode, where there are eight data bits followed by an acknowledge bit). simi- larly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 52 and figure 53). note that the channel of interest is the one that is previously selected in the write mode. in the case where users need to read the rdac values of both channels, they must program the first channel in the write mode and then change to the read mode to read the first channel value. after that, the user must change back to the write mode with the second channel selected and read the second channel value in the read mode. it is not necessary for users to issue the frame 3 data byte in the write mode for subse- quent readback operation. refer to figure 52 and figure 53 for the programming format. following the data byte, the validation byte contains two validation bits, e0 and e1. these bits signify the status of the one-time programming (see figure 52 and figure 53). 4. after all data bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low-to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition (see figure 50 and figure 51). in read mode, the master issues a no acknowledge for the ninth clock pulse (i.e., the sda line remains high). the master then brings the sda line low before the 10 th clock pulse, which goes high to establish a stop condition (see figure 52 and figure 53). a repeated write function gives the user flexibility to update the rdac output a number of times after addressing and instruc- ting the part only once. for example, after the rdac has acknowledged its slave address and instruction bytes in the write mode, the rdac output is updated on each successive byte. if different instructions are needed, the write/read mode has to start again with a new slave address, instruction, and data byte. similarly, a repeated read function of the rdac is also allowed.
ad5172/ad5173 rev. a | page 21 of 24 table 9. valida tion status e 1 e 0 s t a t u s 0 0 r e a d y for progr a m m i n g . 1 0 fatal error. som e fuses not blown. do not retry. discard this unit. 1 1 successful. no further programming i s possi ble. multiple dev i ces on one bus(ad5173 only) f i gur e 54 s h o w s f o ur ad5173s o n the s a m e s e r i al b u s. e a c h has a dif f er en t sla v e addr es s b e c a us e t h e s t a t es o f t h eir ad0 and ad1 p i n s a r e di f f er en t. this al lo ws e a ch de vic e o n t h e b u s t o b e w r itte n to or re a d f rom i n d e p e nd e n t l y . t h e m a ste r d e v i c e o u t p ut b u s li n e dr i v ers a r e o p en-dra i n p u l l -dow n s in a f u l l y i 2 c c o m p a t ibl e i n te r f ac e. sda sda ad1 ad0 master scl scl ad5173 sda ad1 ad0 scl ad5173 sda ad1 ad0 scl ad5173 sda 5v r p r p 5v 5v 5v ad1 ad0 scl ad5173 04103-0-044 f i g u re 54. m u lt ip le a d 51 73s on o n e i 2 c bus
ad5172/ad5173 rev. a | page 22 of 24 pin conf igura t ion and fu nction descriptions 10 9 8 7 1 2 3 4 b1 a1 w2 w1 b2 a2 sda gnd 6 5 scl v dd top view ad5172 04103-0-045 f i gure 55. ad5172 p i n configu r ation 10 9 8 7 1 2 3 4 b1 ad0 w2 w1 b2 ad1 sda gnd 6 5 scl v dd top view ad5173 04103-0-046 f i gure 56. ad5173 p i n configu r ation table 10. a d 5 172 pin fu nction descriptions p i n m e n m o n i c d e s c r i p t i o n 1 b 1 b1 t e r m i n a l . 2 a 1 a1 t e r m i n a l . 3 w 2 w2 t e r m i n a l . 4 g n d digital g r o u n d . 5 v dd positive power s u pply. 6 scl serial clock input. positive edg e triggered. 7 sda serial data inpu t/ output. 8 a 2 a2 t e r m i n a l . 9 b 2 b2 t e r m i n a l . 1 0 w 1 w1 t e r m i n a l . table 11.ad51 73 pin functio n descriptions p i n m n e m o n i c d e s c r i p t i o n 1 b 1 b1 t e r m i n a l . 2 a d 0 programmab l e ad d r ess bit 0 for m u ltiple package decodi ng. 3 w 2 w2 t e r m i n a l . 4 g n d digital g r o u n d . 5 v dd positive power s u pply. 6 scl serial clock input. positive edg e triggered. 7 sda serial data inpu t/ output. 8 a d 1 programmab l e ad d r ess bit 1 for m u ltiple package decodi ng. 9 b 2 b2 t e r m i n a l . 1 0 w 1 w1 t e r m i n a l .
ad5172/ad5173 rev. a | page 23 of 24 outline dimensions 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba f i gure 57. 1 0 -l ead m i ni s m al l o u tl ine p a ck ag e [msop ] (r m - 10) di me nsio ns sho w n i n mi ll im e t e r s
ad5172/ad5173 rev. a | page 24 of 24 orderi ng guide m o d e l r ab (k?) temperature r a nge package descri ption package option branding ad5172brm2.5 2.5 C40c to +125c msop-10 rm-10 d0u ad5172brm2.5- rl7 2.5 C40c to +125c msop-10 rm-10 d0u ad5172brm10 10 C40c to +125c msop-10 rm-10 d0v ad5172brm10- rl7 10 C40c to +125c msop-10 rm-10 d0v ad5172brm50 50 C40c to +125c msop-10 rm-10 d10 ad5172brm50- rl7 50 C40c to +125c msop-10 rm-10 d10 ad5172brm100 100 C40c to +125c msop-10 rm-10 d11 ad5172brm100 -rl7 100 C40c to +125c msop-10 rm-10 d11 ad5172eval 1 e v a l u a t i o n bo ar d ad5173brm2.5 2.5 C40c to +125c msop-10 rm-10 d1k ad5173brm2.5- rl7 2.5 C40c to +125c msop-10 rm-10 d1k ad5173brm10 10 C40c to +125c msop-10 rm-10 d1l ad5173brm10- rl7 10 C40c to +125c msop-10 rm-10 d1l ad5173brm50 50 C40c to +125c msop-10 rm-10 d1m ad5173brm50- rl7 50 C40c to +125c msop-10 rm-10 d1m ad5173brm100 100 C40c to +125c msop-10 rm-10 d1n ad5173brm100 -rl7 100 C40c to +125c msop-10 rm-10 d1n ad5173eval 1 e v a l u a t i o n bo ar d 1 th e eval uat i on board is s h ippe d with the 10 k ? r ab re si st or opt i on ; h o w e ver, t h e boa r d i s com p a t i b le wi t h a ll a v a i l a b le r e si st or va lu e opt i on s. purch a se of li c e n s e d i 2 c com p on en t s o f an a l og d e vi ces or on e of i t s subli c en s e d as soci a t ed c o m p a n i e s con v eys a li cen s e for t h e purch a ser un der t h e ph i li p s i 2 c p a te nt rights to us e the s e co mpo n e nts in an i 2 c sy st em , provi d e d t h a t t h e syst em c o n f orm s t o t h e i 2 c stand a rd speci f ication as d e f i ned by phil ips . ? 2003 a n al og devic e s , inc . a ll righ ts r e ser v e d . t r a d em arks an d r e gist er e d tr ad emar ks ar e the pr oper t y o f their r e spec tiv e o w ners . c04103C0 C 11/03( a )

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